The invention relates to a jumperless computer system.
As people use more office-automation equipment than ever, the majority of users of a highly sophisticated computer system nowadays are layman. Therefore, the trend of the computer system being a user-friendly home appliance, which is observed from current industrial standard such as PC 97, ACPI, is obvious and irreversible.
With respect to a computer system, more and more users wish to configure the computer system within a very short of time. When upgrading the computer system, the user also wishes a simple upgrade procedure.
Most current mother boards of the computer system include a plurality of jumpers which function to adjust the parameters in association with the operation of the computer system. The operation parameters include, for instance, the operation frequency of the processor (CPU), the multiple ratio between the host bus clock and the internal clock, etc. When the jumpers are not adequately set, either the computer system can not boot up or, in a worse situation, some hardware components may be damaged.
We classify the jumpers on the mother board into two categories. The first category of jumpers are those, when incorrectly set up, critical to the successful boot-up of the computer system. The second category of jumpers are those, when incorrectly set up, which diminish the performance of the computer system. Based on the foregoing statements, the invention provides a hardware implementation together with a corresponding software method to tackle this problem.
The main object of the invention aims to handle the first category of jumpers. With the invention, a jumperless mother board or computer system is made possible.
A jumperless computer system is provided. The user might reconfigure the computer system, as a new processor is inserted into a processor socket, through a software approach.
The computer system includes a circuit, responsive to insert of a processor into a socket coupled to the circuit, generating an insert signal.
The insert signal generation circuit includes an insert detection circuit, a trigger means and a register.
The insert detection circuit is connected to the socket for generating a detection signal as the processor is inserted into the socket.
The trigger means is responsive to the detection signal and generates a pulse signal.
The register is responsive to the pulse signal and generates the insert signal.